SystemVerilog game on FPGA with VGA output
Developed a hardware-accelerated Breakout-style game in SystemVerilog, deployed to an FPGA with VGA output. Designed paddle/ball movement, brick collision detection, and screen refresh logic.
Case Study
Problem
Implement a fully playable Breakout clone in hardware with no CPU or OS, where all game logic runs as synchronous digital circuits on an FPGA outputting a live VGA signal.
Architecture
- Top-level SystemVerilog module wiring VGA timing, game FSM, and input controller
- VGA sync generator producing 640×480 @ 60 Hz H/V sync and pixel clock
- Parameterised ball physics module with fixed-point velocity and collision detection
- Paddle controller driven by on-board push buttons with debounce logic
- Brick grid ROM with hit-tracking registers cleared on collision
- Score/lives display using on-screen 7-segment font rendered in logic
Challenges
- Fitting all logic within FPGA LUT budget while meeting 25.175 MHz pixel-clock timing
- Implementing collision detection between a moving ball and a grid of bricks without a CPU
- Handling edge-case ball corner collisions without introducing visual glitches
- Synchronising button input debounce with the VGA frame clock domain
Tradeoffs
- Used fixed-point arithmetic (Q4.4) instead of floating-point to stay within FPGA DSP blocks
- Brick grid stored in registers rather than block RAM for simpler combinatorial hit logic
- Single-speed ball velocity (no acceleration) to keep FSM states manageable
Outcome
Fully playable Breakout game running on FPGA hardware with stable 60 Hz VGA output, correct collision physics, and score tracking.
What I Learned
- VGA timing specification and how to derive sync signals in hardware
- Fixed-point arithmetic design patterns in SystemVerilog
- FSM decomposition for game state (idle, playing, ball lost, win)
- Timing closure techniques: pipeline stages and register retiming in Quartus